Various types of defects and failures can occur during the manufacture of semiconductor devices. A "failure" occurs when a semiconductor device fails to meet its specifications. A "defect" occurs when a semiconductor device has an improper circuit structure that currently presents a failure of the device, or has the potential to fail during the expected lifetime of the device. For example, due to a manufacturing error, an insulator or dielectric such as nitrite between electrodes in a capacitor can be thinned or include pin holes which could currently provide a short or decreased capacitance therebetween, or could break down over a period of time ("a dielectric defect"). After this period of time, typically during prolonged use of the device, the thinned or apertured dielectric provides a conductive path between the electrodes so that a "high" voltage stored on one electrode forces a "low" voltage on the adjacent electrode to rise to a high value, resulting in a failure of the device.
Therefore, an aperture between electrodes that presently reduces the capacitor's ability to hold a charge is a defect resulting in a failure of the semiconductor device. An apertured or thinned dielectric that has not yet formed a sufficient short between the two electrodes, however, is a defect that has not yet evidenced itself as a failure. As a result, the semiconductor device can be operated for a brief time under standard operating conditions and voltages before the defect manifests itself as a failure.
Testing is performed on semiconductor devices to locate defects and failures in such devices. As circuit density on semiconductor devices increases, the number of defects and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect for defects and failures in semiconductor devices as circuit density on these devices increases.
Thus, for quality control and to improve yields of acceptably operable semiconductor devices, semiconductor devices are tested, often before a die containing the semiconductor device is packaged into a chip. A series of probes on a test station electrically contact pads on each die in a wafer to thereby access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory devices ("DRAM") include one or more arrays of memory cells that are each arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit, digit or column lines (or pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
During testing, predetermined data or voltage values are typically written to selected row addresses, or row and column addresses, that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor devices fail the test.
A person testing the several dies on the wafer can then examine a particular die itself, by means of a microscope, to determine if failures occurred from masking defects, during the deposition of certain layers, and so forth. During the initial development of a semiconductor device, and while the device is in die form, changes to masks can be made to compensate for most detected failures. However, once a semiconductor device is in production and packaged as a chip, redundant circuitry on the semiconductor device can be employed to compensate for only certain detected failures. Redundant circuitry on the semiconductor device cannot compensate for many detected failures, and therefore, such failed devices must generally be discarded.
To increase output of acceptable semiconductor devices, semiconductor manufacturers strive to perform rapid testing of the semiconductor devices to expose defects in the devices before shipping them to a vendor or user. A semiconductor device can be most thoroughly tested when the device is still in die form on the semiconductor wafer. Semiconductor wafers, however, are often difficult to manipulate, and typically require a test bed or other apparatus to releasably secure the wafer while the probes are adjusted to contact the pads on each die on the wafer. As a result, testing of semiconductor devices in die form is time consuming. Therefore, semiconductor manufacturers desire to test a given semiconductor device after it has been packaged as a semiconductor chip, because the chip can be automatically inserted into a test socket for testing using pick and place machinery. Automated testing circuitry can then apply predetermined voltages and signals to the chip, write test patterns thereto, and analyze the results therefrom to detect for failures in the chip.
Often, the number of pads on a die is greater than the number of pins on the packaged semiconductor chip. Therefore, as noted above, certain tests performed while the semiconductor device is in die form cannot be performed on the device after it has been packaged. As a result, package chips necessarily undergo less rigorous testing than unpackaged dies. Packaged chips can include manufacturing defects that are not yet failures and thus are undetectable by the limited number of tests capable of being performed on the packaged chips.
For example, in typical semiconductor memory devices, such as DRAMs, the capacitor in each memory cell has a "storage electrode" that stores a voltage value representing the data written to the memory cell (a high voltage value indicating a logical "1" value and a low voltage value indicating a logical "0" value). "Ground" electrodes for each of the capacitors are typically electrically intercoupled at a "DVC2 node" as a single conductive layer in the semiconductor device to form a "cell plate." The DVC2 node is typically maintained at a voltage value approximately half that of the positive supply voltage or Vcc/2 to thereby provide a maximum voltage differential between the storage and cell plates of each capacitor, regardless of whether a high or low voltage is written to the storage plate.
To test for the dielectric defect discussed above, a test circuit writes low voltage values (as logical "0" values) to all capacitors in the memory cells of the memory cell array. The test circuit thereafter raises the voltage at the DVC2 node to a voltage value approximately equal to Vcc. The test circuit then determines whether all the memory cells have maintained a logical "0"value. If not, then the "high" voltage value applied to the DVC2 node has leaked or shorted to the storage plate of a capacitor in a memory cell, causing the low voltage or logical "0" value initially stored thereon to rise and become a high voltage or logical "1" value.
The time required for the high voltage value on the DVC2 node to raise the voltage on the storage plate of a capacitor will vary depending upon the severity of the defect in the dielectric between the cell and storage plates. As a result, a high voltage value over a continuous period of time must be applied to the DVC2 node to force the failure in one or more of the memory cells in the semiconductor device. External test circuitry typically must apply such a continuous, high voltage value to the semiconductor memory device while the device is still in its die form.
Many semiconductor memory devices include an on-chip voltage pump that provides the Vcc/2 voltage to the DVC2 node. The on-chip voltage pump, however, typically does not have the capacity to raise the voltage of the DVC2 node well beyond the Vcc/2 value for a prolonged period of time. Consequently, dielectric defects cannot be efficiently tested in packaged chips. As a result, dielectric defects can typically only be tested efficiently when the semiconductor memory device is in die form. Probes access the DVC2 node and apply supplemental power to the device being tested to thereby provide the high voltage value to the cell plate over the continuous test period. Such a dielectric stress test, however, suffers from the above-described difficulties in testing semiconductor memory circuits when in die form. Therefore, while such a test is desirable, its value is offset by the time consuming process of manipulating and testing semiconductor wafers.